This is experimental and work in progress! If you find crashes or unsupported features, please report them!
v0.37, GHDL features a built-in (experimental) synthesis kernel with two backends:
yosys-plugin. Currently, synthesis is supported as a front-end of other synthesis and technology mapping tools.
Hence, the netlists generated by GHDL are not optimised.
Due to GHDL’s modular architecture (see Overview), the synthesis kernel shares the VHDL parsing front-end with the simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration (see Options).
This command is useful for checking that a design can be synthesized, before actually running a complete synthesis tool. In fact, because this is expected to be much faster, it can be used as a frequent check.
Since GHDL’s front-end supports multiple versions of the standard, but the synthesised netlists are generated using a subset of VHDL 1993, GHDL’s synthesis features can be used as a preprocessor with tools that do support older versions of the standard, but which don’t provide the most recent features.
<[options] primary_unit [secondary_unit]>¶
Elaborates for synthesis the design whose top unit is indicated by
All the units must have been analyzed; that is, the artifacts of previously executed
-a calls must exist.
<[options] files... -e primary_unit [secondary_unit]>¶
Analyses and elaborates for synthesis the files present on the command line only.
Elaboration starts from the top unit indicated by
Currently, the output is a generic netlist using a (very simple) subset of VHDL 1993. See #1174 for on-going discussion about other output formats.
Files can be provided in any order.
ghdl-yosys-plugin is a module to use GHDL as a VHDL front-end for Yosys Open Synthesis Suite, a framework for optimised synthesis and technology mapping. Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification, etc. A relevant feature of combining GHDL and Yosys is that mixed-language (VHDL-Verilog) synthesis with open source tools is possible.
The command line syntax for this plugin is the same as for
--synth, except that the command name (
is neither required nor supported. Instead,
yosys -m ghdl or
yosys -m path/to/ghdl.so need to be used,
depending of how is the plugin built. See README for building and installation