Heartbeat module

Although Hello world illustrates that VHDL is supported as a general purpose language, the main use case of GHDL is to simulate hardware descriptions. The following block, which is saved in a file named heartbeat.vhdl, is an example of how to generate a 100 MHz clock signal with non-synthesisable VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity heartbeat is
  port ( clk: out std_logic);
end heartbeat;

architecture behaviour of heartbeat
  constant clk_period : time := 10 ns;
  -- Clock process definition
  clk_process: process
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
end behaviour;

It can be analysed, elaborated and run, as you already know:

ghdl -a heartbeat.vhdl
ghdl -e heartbeat
ghdl -r heartbeat

However, execution of the design does not terminate. At the same time, no output is shown on screen. This is because, traditionally, hardware designs are continuously running devices which do not have a screen where to print. In this context, inspection and verification of the behaviour is done through waveforms, which is supported by GHDL (see Export waveforms). You can use either --wave, --vcd, --vcdgz or --fst to save the signals of the simulation to a file. Then, terminate the execution (C-c) and you can inspect the wave with a viewer, such as GtkWave. As explained in the manual, GtkWave ‘relies on a post-mortem approach through the use of dumpfiles’. Therefore, you should first simulate your design and dump a waveform file, say GHW:

ghdl -r heartbeat --wave=wave.ghw

Then, you can view the dump:

gtkwave wave.ghw

Of course, manually terminating the simulation is for illustration purposes only. In Full adder and Working with non-trivial designs, you will see how to write a testbench to terminate the simulation programmatically.