What is VHDL?¶
VHDL is an acronym for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (HDL), which is a programming language used to describe a logic circuit by function, data flow behavior, or structure.
Although VHDL was not designed for writing general purpose programs, VHDL is a programming language, and you can write any algorithm with it. If you are able to write programs, you will find in VHDL features similar to those found in procedural languages such as C, Python, or Ada. Indeed, VHDL derives most of its syntax and semantics from Ada. Knowing Ada is an advantage for learning VHDL (it is an advantage in general as well).
However, VHDL was not designed as a general purpose language but as an HDL. As the name implies, VHDL aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an event-based timing model.
Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term simulation is often used instead of execution, with the same meaning. At the same time, like a design written in another HDL, a set of VHDL sources can be transformed with a synthesis tool into a netlist, that is, a detailed gate-level implementation.
The development of VHDL started in 1983 and the standard is named IEEE 1076. Four revisions exist: 1987, 1993, 2002 and 2008. The standardization is handled by the VHDL Analysis and Standardization Group (VASG/P1076).
What is GHDL?¶
GHDL is a shorthand for G Hardware Design Language (currently, G has no meaning). It is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet).
Unlike some other simulators, GHDL is a compiler: it directly translates a VHDL file to machine code, without using an intermediary language such as C or C++. Therefore, the compiled code should be faster and the analysis time should be shorter than with a compiler using an intermediary language.
The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. You can still check the behavior of your design with a test bench. Moreover, the current version can produce a GHW, VCD or FST files which can be viewed with a waveform viewer, such as GtkWave.
Although synthesis is not supported yet, there is some experimental code. On the one hand, subcommand
--synth is a proof-of-concept to generate a netlist (RTL) with GHDL. For now, it is a dump of an internal structure, so it is not very useful, except for debugging. In the future, it might be an EDIF or VHDL file. On the other hand, ghdlsynth is a complementary repository that allows GHDL to be loaded by yosys as a module, which can be used to generate bitstreams for some FPGA devices.